<![CDATA[I-Connect007: Advanced Electronics Packaging Digest]]>https://iconnect007.substack.com/s/advanced-electronics-packaging-digesthttps://substackcdn.com/image/fetch/$s_!s1lm!,w_256,c_limit,f_auto,q_auto:good,fl_progressive:steep/https%3A%2F%2Fsubstack-post-media.s3.amazonaws.com%2Fpublic%2Fimages%2F66680d13-d0cc-4b34-a7dc-bb458a53fa1c_706x706.pngI-Connect007: Advanced Electronics Packaging Digesthttps://iconnect007.substack.com/s/advanced-electronics-packaging-digestSubstackTue, 19 May 2026 20:11:47 GMT<![CDATA[AEPD May 2026]]>https://iconnect007.substack.com/p/subscriber-early-access-aepd-mayhttps://iconnect007.substack.com/p/subscriber-early-access-aepd-mayFri, 15 May 2026 19:57:42 GMT
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Rethinking Reinforcement Materials for Advanced Packaging

Ivana Ivanovic, Flexiramics B.V.

Materials that once quietly supported the industry are now becoming limiting factors. The electronics industry is experiencing unprecedented pressure as RF systems push into mmWave frequencies, high-speed digital architectures advance into their next performance generation, and power densities climb across automotive, telecom, aerospace, and computing. Reinforcement materials, long treated as a background detail in laminate design, are suddenly at the centre of performance, reliability, and supply‑chain discussions.

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System Architecture Beyond the Die With Advanced Packaging as the Scaling Factor

Chetan Arvind Patil, Marvell Technology

In conventional monolithic semiconductor design, system integration was achieved within a single die and constrained by reticle limits. Compute cores, cache, memory controllers, and input output (I/O) interfaces were all co-optimized on a single process node, with performance closely tied to transistor density and on-die interconnect efficiency. This monolithic system-on-chip (SoC) approach enabled low-latency communication and relatively straightforward power delivery. However, as design for compute-intensive SoCs approaches reticle limits and advanced-node costs increase, the ability to continue scaling within a single die begins to diminish.

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What Heterogeneous Integration Means for EMS Providers

Nolan Johnson, I-Connect007

Dr. Ravi Mahajan, an Intel Fellow and Director of Intel’s Technology and Pathfinding group, delivered a keynote at the APEX EXPO 2026 technical conference on using heterogeneous integration (HI) as a strategy and on how advanced packaging technology serves as the technical apex for implementing that strategy. Mahajan’s previous papers and industry presentations on such topics as interconnect density, signal integrity, power delivery, thermal path, and assembly yield as system-level constraints confirm him as an expert on package optimization.

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]]><![CDATA[AEPD April 2026]]>https://iconnect007.substack.com/p/aepd-april-2026https://iconnect007.substack.com/p/aepd-april-2026Mon, 20 Apr 2026 20:18:16 GMT

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Advanced Packaging for AI: Reliability Starts at the Cu/Cu/Cu Microvia Junction

Kuldip Johal, MKS’ Atotech

The rapid growth of AI computing, from training clusters to inference at scale, is reshaping demand across the entire electronics supply chain. Advances in technology requirements, such as higher bandwidth, lower latency, and greater compute density, are driving the development of advanced packaging technologies and transforming the PCB industry across design, manufacturing, testing, and even architecture.

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Single Pair Ethernet (SPE): A Valuable Option for Modern Designs

Marcy LaRont, I-Connect007

When it comes to designing PCBs and full systems for increasingly complex electronics hardware, who doesn’t want to reduce complexity and cost? Single-Pair Ethernet (SPE) has emerged as a solution and is gaining rapid attention across industrial electronics and PCB design because it enables Ethernet communication over a single twisted pair, replacing the traditional two- or four-pair cabling used in standard Ethernet networks. This seemingly simple shift has significant implications for designers: smaller connectors, reduced cable weight, longer reach, and the ability to carry both data and power over a single pair.

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Webinar Review, Part 2: Building the AI Backbone at IBM on Systems-level Packaging

Marcy LaRont, I-Connect007

The second presentation in a recent Global Electronics Association’s Executive Pulse webinar series widened the lens on advanced packaging, moving beyond the component level to a systems-level view of how AI is reshaping the electronics landscape. Building on Dr. Hemanth Dhavaleswarupu of AMD’s previous discussion of chip-level packaging innovation, Dr. Jung Yoon of IBM explored the broader infrastructure implications, from the data center floor to the global supply chain.

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]]><![CDATA[COMING MONDAY APRIL 20]]>https://iconnect007.substack.com/p/coming-monday-april-20https://iconnect007.substack.com/p/coming-monday-april-20Mon, 13 Apr 2026 19:45:51 GMT

AI Is Redefining Advanced Packaging. Here’s What’s Next.

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AI is reshaping the entire electronics ecosystem, from materials and interconnects to system-level architecture.

In the upcoming issue of Advanced Electronics Packaging Digest, we explore the technologies driving this shift—and what they mean for designers, manufacturers, and the broader supply chain.

Here’s a preview of what’s inside:

  • Reliability at the micro level: Why the Cu/Cu/Cu microvia junction is emerging as a critical point in AI-driven designs, where performance and long-term reliability are on the line

  • Smarter, simpler connectivity: How Single Pair Ethernet (SPE) is gaining traction as a streamlined, high-performance solution for increasingly compact systems

  • A systems-level perspective: Insights from IBM on how AI is influencing packaging strategies, infrastructure, and the future of electronics at scale

The takeaway? Innovation isn’t happening in silos. It’s happening across the entire stack—and the companies that understand those connections will be the ones that lead.

The full issue drops on Substack on April 20.

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]]><![CDATA[AEPD March 2026]]>https://iconnect007.substack.com/p/aepd-march-2026https://iconnect007.substack.com/p/aepd-march-2026Thu, 26 Mar 2026 18:52:49 GMT

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IC Substrates vs. UHDI: The Future of Interconnect

Marcy LaRont, I-Connect007

Advanced packaging is driving feature sizes below 50 microns, forcing IC substrates and UHDI PCBs into overlapping territory. Following his presentation at the Pan-European Design Conference (PEDC) in January, Jan Pedersen, director of technology at NCAB Group, spoke with us about how heterogeneous integration, evolving HDI roadmaps, and supply chain pressures are shaping the next phase of advanced packaging.

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Webinar Review, Part 1: A Packaging Revolution Powering the Next Era of AI Compute

Marcy LaRont, I-Connect007

The rapid rise of artificial intelligence has fundamentally reshaped the demands placed on semiconductor technology, and nowhere is it more evident than in advanced electronic packaging. A recent episode of the Global Electronics Association’s Executive Pulse webinar series, featuring Dr. Hemanth Dhavaleswarapu of AMD as the first of two esteemed presenters, provided a comprehensive overview of chip-level packaging. He outlined the evolution of AI workloads in forcing a rethinking of everything from chip architecture to data center design, with packaging now playing a central role in enabling continued performance scaling.

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Below the Surface: From Substrate to System—Why Integration Is the Real RF Breakthrough

Chandra Gupta

In my last column, I described the ceramic substrate itself, and why material choice matters so deeply in RF, microwave, and millimeter-wave applications. Dielectric constant, loss tangent, thermal conductivity, stability across temperature, and frequency are the physical rules that govern whether a signal arrives intact or collapses into noise.

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]]><![CDATA[AEPD February 2026]]>https://iconnect007.substack.com/p/february-2026-aepdhttps://iconnect007.substack.com/p/february-2026-aepdMon, 16 Feb 2026 19:42:29 GMT

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Changing the Electronics Systems Conversation

Nolan Johnson, SMT007 Magazine

Rebranding as the Global Electronics Association is not the only major change happening at APEX EXPO this year. There’s also a shift in the scope of the technical program as heterogenous integration and other advanced packaging methodologies come into the mainstream at both the component and system levels. We spoke with Matt Kelly, CTO and conference general chair, Devan Iyer, chief strategist for advanced electronic packaging, and Stan Rak and Udo Welzel, now in their fourth year as chairs of the Technical Program Committee, about what distinguishes the conference this year.

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UHDI Fundamentals—Foundations and Drivers of the PCB Flex: Advanced Packaging Nexus, Part 1

Anaya Vardya, American Standard Circuits

The electronics industry is undergoing a fundamental transformation driven by demands for smaller form factors, higher performance, and greater functional integration. Two technologies sit at the center of this transformation: flexible PCBs and advanced semiconductor packaging. In this article, I’ll explore the technical foundations and key forces driving this convergence. Flexible PCBs are electrical interconnects fabricated on bendable substrates such as polyimide or polyester. Unlike rigid PCBs, flex circuits can conform to three-dimensional shapes, enabling designers to route signals through space rather than across flat planes

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Designers Notebook: Heterogeneous Interposer Design Challenge, Part 2

Vern Solberg

As the need grows for higher processing speed and the expanded functionality required for newer generations of central processing units (CPUs), the necessity for higher-density interconnect solutions is paramount. The current trend toward furnishing a single, monolithic system-level semiconductor package has become a serious yield issue in fabrication. For example, with all of the peripheral supporting functions on a single die platform, wafer fabrication yields are often below target and, although the CPU portion of a monolithic semiconductor may be perfect, if one or more of the supporting functions on the same die fails, the entire processor unit must be discarded.

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