<![CDATA[I-Connect007: Advanced Electronics Packaging Digest]]>https://iconnect007.substack.com/s/advanced-electronics-packaging-digesthttps://substackcdn.com/image/fetch/$s_!n1Rq!,w_256,c_limit,f_auto,q_auto:good,fl_progressive:steep/https%3A%2F%2Fsubstack-post-media.s3.amazonaws.com%2Fpublic%2Fimages%2F966b4e31-51f6-498c-a9a8-a352d4a8d3b9_256x256.pngI-Connect007: Advanced Electronics Packaging Digesthttps://iconnect007.substack.com/s/advanced-electronics-packaging-digestSubstackMon, 24 Aug 2026 16:09:45 GMT<![CDATA[AEPD August 2026]]>https://iconnect007.substack.com/p/aepd-august-2026https://iconnect007.substack.com/p/aepd-august-2026Fri, 14 Aug 2026 15:45:16 GMT
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A Better Way to Characterize Copper Foils for Flexible Printed Circuits, Advanced Packaging

Nolan Johnson, I-Connect007

Finite element analysis is only as accurate as the material properties behind it. Kenji Koike discusses research showing that digital image correlation produces more precise stress-strain curves and Young’s modulus measurements for rolled copper foils, giving engineers greater confidence when designing flexible printed circuits and advanced packaging for demanding applications.

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More Than Moore Enabled by Advanced Packaging and Heterogeneous Integration

Chetan Arvind Patil, Marvell Technology

For more than a half-century, Moore’s Law has been the defining principle of semiconductor innovation. By continually shrinking transistor dimensions, the semiconductor industry delivered exponential improvements in computing performance, energy efficiency, and integration density. Each new technology node enabled more transistors to be placed on a single die, reducing the cost per transistor and making electronic systems smaller, faster, and more capable. Though this scaling continues to advance, it is no longer the sole driver of system-level innovation, which now increasingly comes from a combination of scaling and advanced packaging.

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Advanced Electronic Packaging: The Industry’s New Innovation Engine

Marcy LaRont, I-Connect007

Over the past several years, advanced packaging has moved from the back end of semiconductor manufacturing to becoming one of the electronics industry’s most strategic technologies in the ecosystem. At many IEEE conferences, discussions that once centered almost exclusively on transistor scaling now devote equal attention to chiplets, heterogeneous integration, co-design, advanced substrates, thermal management, and system-level packaging.

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Below the Surface: Why Thermal Failure Is Still the No. 1 Killer in Power Electronics

Chandra Gupta

Why do power electronics fail? There’s a range of answers, from overvoltage and mechanical stress to poor assembly and environmental exposure. If you ask your favorite AI search engine for an answer, you’ll get a pretty simple response: excessive temperature leads to component degradation, material breakdown, and eventual failure. In a sense, that’s true, but it’s oversimplified and incomplete. The real issue is thermal management failure at the system level. Heat is still the number one killer, and most of the time, you don’t even realize it’s there.

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]]><![CDATA[AEPD July 2026]]>https://iconnect007.substack.com/p/aepd-july-2026https://iconnect007.substack.com/p/aepd-july-2026Fri, 17 Jul 2026 15:14:47 GMT
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Power and Thermal Constraints in AI Accelerator Packages

Chetan Arvind Patil, Marvell Technology

For more than five decades, semiconductor progress was driven primarily by transistor scaling. Moore’s Law provided a predictable path for increasing transistor density, while process technology advancements consistently improved performance, power efficiency, and manufacturing cost. During this period, package development evolved alongside silicon, supporting higher pin counts, faster interfaces, and improved thermal performance, but it rarely dictated overall system capability.

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The AI Data Center Boom: Technology, Capacity, and Society

Marcy LaRont, I-Connect007

AI begins with advanced chips, but delivering AI at scale depends on an ecosystem of technologies that extends far beyond the semiconductor. In this interview, Andrew Bradner, senior vice president of Schneider Electric’s cooling business, explains how AI is transforming data center design, why liquid cooling has become essential, and what these shifts mean for advanced packaging, power delivery, thermal management, and the broader electronics supply chain supporting next-generation AI infrastructure.

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Below the Surface: Ceramic vs PCB—When ‘Good Enough’ Becomes System Failure

Chandra Gupta

Let’s start with the question engineers are increasingly asking themselves: “When should I use ceramic instead of FR-4?” It’s a fair question. FR-4 has been the backbone of electronics for decades. It’s affordable, widely available, and for many applications, it works just fine. Until it doesn’t.

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Call for Participation Now Open for the Global Electronics Association’s Advanced Electronic Packaging Conference at APEX EXPO 2027

Global Electronics Association

AEPC is the electronics industry’s premier technical conference for component-to-system-level integration, advanced PCB and assembly manufacturing, and next-generation electronics technologies. The Global Electronics Association invites engineers, researchers, manufacturers, and technology leaders from around the world to submit technical presentation abstracts for this distinguished event.

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]]><![CDATA[AEPD June 2026]]>https://iconnect007.substack.com/p/early-access-aepd-june-2026https://iconnect007.substack.com/p/early-access-aepd-june-2026Fri, 12 Jun 2026 15:28:10 GMT
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Thermoreflectance and Solving the Thermal Puzzle in 3D Packaging

Marcy LaRont, I-Connect007

Advanced packaging and 3D heterogeneous integration are rapidly redefining the next phase of the semiconductor industry, delivering unprecedented performance gains while posing significant thermal management challenges. In this interview, Dr. Mohammad (Mo) Shakouri, founder and CEO of Microsanj, discusses how thermoreflectance-based metrology is enabling engineers to visualize and measure heat behavior at the nanoscale within complex packages, interposers, and TSV structures.

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Getters for Hermetic Packages: Mechanisms, Reliability Impact, and MacDermid Alpha Electronics Solutions

Michael Previti, MacDermid Alpha Electronics Solutions

Hermetic packages protect chips, lasers, and sensors from the outside world, but the cavity inside can still change after seal. Small amounts of water, hydrogen, carbon dioxide, and organic vapor may remain after build or may form later from adhesives, films, and other internal materials. Getters reduce that risk by creating a planned sink for those gases inside the package. When teams choose the right getter early, they hold the headspace steady, cut reliability escapes, and lower the life-cycle cost of a high-value device.

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Advanced Packaging: A Central Axis of Innovation in A&D, Automotive

I-Connect007 Editorial Team

Presenters in the Aerospace & Defense Special Session at APEX EXPO 2026 made one message abundantly clear: Advanced packaging has moved from a supporting role to a primary system enabler, particularly in high-reliability markets where performance, longevity, and environmental resilience are non-negotiable. The March Technical Conference at APEX EXPO focused on advanced electronics for the first time this year, with two Special Sessions featuring a carefully curated selection of presentations examining how design priorities, material choices, and manufacturing strategies are evolving in response to these demands.

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Below the Surface: From Nanometers to 10-Gauge—It’s More Than Just a Wire

Chandra Gupta, Remtec

Modern life runs on wires: your cell phone, your car, the satellites orbiting above us, and even the dryer in your laundry room all depend on the simple idea of moving electricity from one place to another. From nanometer-scale traces etched onto a semiconductor chip to a thick 10-gauge copper wire carrying current to heat your clothes, it’s tempting to say, “It’s just a wire.” But that hides the real story. The magic isn’t the wire itself, but in the materials that insulate, protect, support, and connect it, often under extreme conditions of heat, voltage, vibration, and time.

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]]><![CDATA[AEPD May 2026]]>https://iconnect007.substack.com/p/subscriber-early-access-aepd-mayhttps://iconnect007.substack.com/p/subscriber-early-access-aepd-mayFri, 15 May 2026 19:57:42 GMT
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Rethinking Reinforcement Materials for Advanced Packaging

Ivana Ivanovic, Flexiramics B.V.

Materials that once quietly supported the industry are now becoming limiting factors. The electronics industry is experiencing unprecedented pressure as RF systems push into mmWave frequencies, high-speed digital architectures advance into their next performance generation, and power densities climb across automotive, telecom, aerospace, and computing. Reinforcement materials, long treated as a background detail in laminate design, are suddenly at the centre of performance, reliability, and supply‑chain discussions.

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System Architecture Beyond the Die With Advanced Packaging as the Scaling Factor

Chetan Arvind Patil, Marvell Technology

In conventional monolithic semiconductor design, system integration was achieved within a single die and constrained by reticle limits. Compute cores, cache, memory controllers, and input output (I/O) interfaces were all co-optimized on a single process node, with performance closely tied to transistor density and on-die interconnect efficiency. This monolithic system-on-chip (SoC) approach enabled low-latency communication and relatively straightforward power delivery. However, as design for compute-intensive SoCs approaches reticle limits and advanced-node costs increase, the ability to continue scaling within a single die begins to diminish.

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What Heterogeneous Integration Means for EMS Providers

Nolan Johnson, I-Connect007

Dr. Ravi Mahajan, an Intel Fellow and Director of Intel’s Technology and Pathfinding group, delivered a keynote at the APEX EXPO 2026 technical conference on using heterogeneous integration (HI) as a strategy and on how advanced packaging technology serves as the technical apex for implementing that strategy. Mahajan’s previous papers and industry presentations on such topics as interconnect density, signal integrity, power delivery, thermal path, and assembly yield as system-level constraints confirm him as an expert on package optimization.

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]]><![CDATA[AEPD April 2026]]>https://iconnect007.substack.com/p/aepd-april-2026https://iconnect007.substack.com/p/aepd-april-2026Mon, 20 Apr 2026 20:18:16 GMT

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Advanced Packaging for AI: Reliability Starts at the Cu/Cu/Cu Microvia Junction

Kuldip Johal, MKS’ Atotech

The rapid growth of AI computing, from training clusters to inference at scale, is reshaping demand across the entire electronics supply chain. Advances in technology requirements, such as higher bandwidth, lower latency, and greater compute density, are driving the development of advanced packaging technologies and transforming the PCB industry across design, manufacturing, testing, and even architecture.

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Single Pair Ethernet (SPE): A Valuable Option for Modern Designs

Marcy LaRont, I-Connect007

When it comes to designing PCBs and full systems for increasingly complex electronics hardware, who doesn’t want to reduce complexity and cost? Single-Pair Ethernet (SPE) has emerged as a solution and is gaining rapid attention across industrial electronics and PCB design because it enables Ethernet communication over a single twisted pair, replacing the traditional two- or four-pair cabling used in standard Ethernet networks. This seemingly simple shift has significant implications for designers: smaller connectors, reduced cable weight, longer reach, and the ability to carry both data and power over a single pair.

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Webinar Review, Part 2: Building the AI Backbone at IBM on Systems-level Packaging

Marcy LaRont, I-Connect007

The second presentation in a recent Global Electronics Association’s Executive Pulse webinar series widened the lens on advanced packaging, moving beyond the component level to a systems-level view of how AI is reshaping the electronics landscape. Building on Dr. Hemanth Dhavaleswarupu of AMD’s previous discussion of chip-level packaging innovation, Dr. Jung Yoon of IBM explored the broader infrastructure implications, from the data center floor to the global supply chain.

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]]><![CDATA[AEPD March 2026]]>https://iconnect007.substack.com/p/aepd-march-2026https://iconnect007.substack.com/p/aepd-march-2026Thu, 26 Mar 2026 18:52:49 GMT

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IC Substrates vs. UHDI: The Future of Interconnect

Marcy LaRont, I-Connect007

Advanced packaging is driving feature sizes below 50 microns, forcing IC substrates and UHDI PCBs into overlapping territory. Following his presentation at the Pan-European Design Conference (PEDC) in January, Jan Pedersen, director of technology at NCAB Group, spoke with us about how heterogeneous integration, evolving HDI roadmaps, and supply chain pressures are shaping the next phase of advanced packaging.

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Webinar Review, Part 1: A Packaging Revolution Powering the Next Era of AI Compute

Marcy LaRont, I-Connect007

The rapid rise of artificial intelligence has fundamentally reshaped the demands placed on semiconductor technology, and nowhere is it more evident than in advanced electronic packaging. A recent episode of the Global Electronics Association’s Executive Pulse webinar series, featuring Dr. Hemanth Dhavaleswarapu of AMD as the first of two esteemed presenters, provided a comprehensive overview of chip-level packaging. He outlined the evolution of AI workloads in forcing a rethinking of everything from chip architecture to data center design, with packaging now playing a central role in enabling continued performance scaling.

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Below the Surface: From Substrate to System—Why Integration Is the Real RF Breakthrough

Chandra Gupta

In my last column, I described the ceramic substrate itself, and why material choice matters so deeply in RF, microwave, and millimeter-wave applications. Dielectric constant, loss tangent, thermal conductivity, stability across temperature, and frequency are the physical rules that govern whether a signal arrives intact or collapses into noise.

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]]><![CDATA[AEPD February 2026]]>https://iconnect007.substack.com/p/february-2026-aepdhttps://iconnect007.substack.com/p/february-2026-aepdMon, 16 Feb 2026 19:42:29 GMT

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Changing the Electronics Systems Conversation

Nolan Johnson, SMT007 Magazine

Rebranding as the Global Electronics Association is not the only major change happening at APEX EXPO this year. There’s also a shift in the scope of the technical program as heterogenous integration and other advanced packaging methodologies come into the mainstream at both the component and system levels. We spoke with Matt Kelly, CTO and conference general chair, Devan Iyer, chief strategist for advanced electronic packaging, and Stan Rak and Udo Welzel, now in their fourth year as chairs of the Technical Program Committee, about what distinguishes the conference this year.

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UHDI Fundamentals—Foundations and Drivers of the PCB Flex: Advanced Packaging Nexus, Part 1

Anaya Vardya, American Standard Circuits

The electronics industry is undergoing a fundamental transformation driven by demands for smaller form factors, higher performance, and greater functional integration. Two technologies sit at the center of this transformation: flexible PCBs and advanced semiconductor packaging. In this article, I’ll explore the technical foundations and key forces driving this convergence. Flexible PCBs are electrical interconnects fabricated on bendable substrates such as polyimide or polyester. Unlike rigid PCBs, flex circuits can conform to three-dimensional shapes, enabling designers to route signals through space rather than across flat planes

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Designers Notebook: Heterogeneous Interposer Design Challenge, Part 2

Vern Solberg

As the need grows for higher processing speed and the expanded functionality required for newer generations of central processing units (CPUs), the necessity for higher-density interconnect solutions is paramount. The current trend toward furnishing a single, monolithic system-level semiconductor package has become a serious yield issue in fabrication. For example, with all of the peripheral supporting functions on a single die platform, wafer fabrication yields are often below target and, although the CPU portion of a monolithic semiconductor may be perfect, if one or more of the supporting functions on the same die fails, the entire processor unit must be discarded.

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